The present invention relates generally to supply voltage monitoring circuits for use in detecting that of two supply voltages is higher in an integrated circuit containing circuitry which otherwise can be damaged if the two supply voltages are increased or “powered up” in the wrong sequence. More particularly, the invention relates to monitoring and switching circuitry that automatically connects the N-type well regions of P-channel transistors to the higher of the two or more supply voltages.
In a mixed-signal system, i.e., a system including both digital signals and analog signals, it is common for the associated digital circuitry and analog circuitry to be powered by separate power supply voltage sources having different voltage levels, for example 5 volts for the analog circuitry and 3.3 volts for the digital circuitry. However, often the digital circuitry that interfaces with the mixed-signal system is powered by a 5 volt supply voltage. The 3.3 volt digital input/output circuitry of the mixed-signal system must be “tolerant” to the 5 volt digital signals received from the above-mentioned external digital circuitry. That is, the 5 volt digital signals must not damage the 3.3 volt digital input/output circuitry. Translation buffer circuits can be used that translate the 5 volt output signals produced by such digital circuitry to the 3.3 volt level required by the digital circuitry in the mixed-signal system. However, use of such translation buffer circuits involves additional cost. In order to accomplish this, the 3.3 volt digital circuitry in the mixed-signal system must be powered by a 5 volt supply.
FIG. 1A shows a schematic view of a typical 3.3V I/O cell 10 which is connected to a generalized I/O cell control circuit. In I/O (input/output) cell 10 the bulk terminal BP and the source terminal SP of a P-channel output driver transistor 13 are connected to a 3.3V digital power supply voltage DVDD. The drain terminal DP of transistor 13 is coupled to a static protection device and to an I/O pad and also to the drain terminal DN of an N-channel transistor 14, the bulk terminal BN and source terminal SN of which are connected to ground.
FIG. 1B shows a cross-sectional view of I/O cell 10 formed in a P-type substrate 12. N-channel transistor 14 has its source and drain comprised of two N-type regions NP formed in substrate 12, the gate of transistor 14 being designated by GN. Electrical contact to P-type substrate 12 is accomplished through heavily doped contact region PP designated by reference numeral 12A. An N-type “well” region 11 is formed in substrate 12, and P-channel transistor 13 is formed by two P-type regions PP formed in well region 11. N-type well region 11 constitutes the bulk terminal of P-channel transistor 13. Electrical contact to well region 11 is accomplished by a heavily doped N-type region NP designated by reference numeral 11A. PN junctions that are formed by the P-type source and drain regions PP of transistor 13 and the N-type well region 11 constitute the two parasitic PN junction diodes D1 and D2, respectively.
I/O cell 10 is not tolerant to a 5 volt input signal applied to the I/O pad because the parasitic diode D1 will become forward-biased every time the I/O pad voltage rises above the DVDD level of 3.3 volts. The forward-biasing of parasitic junction diode D1 will not only conduct a large amount of current through it but it may also cause latch-up and/or permanent damage to the I/O cell. As is well-known to those skilled in the art, integrated circuit structures often include parasitic bipolar transistors that interact in a regenerative fashion to switch a parasitic latch circuit into a high-current mode as a result of forward-biasing of a parasitic PN junction. The resulting high current may damage the integrated circuit. In any case, the parasitic latch device can be switched off so as to eliminate the high current only by removing power from the circuit before turning the power back on to continue operation of the circuit.
Referring to FIG. 1C and the corresponding integrated circuit sectional view in FIG. 1D, in order to make the 3.3V I/O cell 10A tolerant to a 5 volt input, N-type well 11 must be at the 5 volt supply level AVDD to avoid forward biasing parasitic diode D1, and this can be accomplished by simply connecting the bulk terminal BP of transistor 13 to the 5 volt analog power supply AVDD. However, this connection requires the user to turn on the analog supply voltage AVDD before the digital supply voltage DVDD during the power-up sequence, and also to turn off the digital supply DVDD before the analog supply AVDD during the power-down sequence. If the foregoing power-up and power-down sequences are not observed, parasitic junction diode D2 will become forward-biased, causing it to conduct a large amount of current through the diode D2, and may also cause latch-up and/or permanent damage to I/O cell 10. The foregoing restriction on the power-up sequence and power-down sequence of the analog and digital power supply voltages limits the convenience of using the dual supply mixed-signal system of FIG. 1C. In a system wherein the sequence of activating power supply voltages cannot be readily controlled, the usefulness of the circuit shown in FIG. 1C is limited. To remove this restriction, it is necessary to have a circuit to keep N-type well 11 at the higher of the two power supply voltages at all times.
FIG. 1E shows a 3.3 volt I/O cell 10B with the bulk terminal BP of the P-channel output driver transistor 13 connected to a monitor circuit 15 which monitors both the 3.3 volt digital supply DVDD and the 5 volt analog supply AVDD and outputs the higher of the two supply voltages to the bulk terminal BP of transistor 13. In I/O cell 10B the parasitic PN junction diodes D1 and D2 can never become forward-biased. I/O cell 10B therefore is “5 volt tolerant” and imposes no restriction on the AVDD and DVDD power-up and power-down sequences
A prior art implementation of monitor circuit 15 of FIGS. 1E and 1F for keeping the N-type well region 11 at the higher of two power supply voltages VA and VB is shown in FIG. 2. The circuit includes cross-coupled P-channel transistors MP1 and MP2 having their drains connected to VABMAX conductor 15A. The gate of transistor MP1 and the source of transistor MP2 are connected to VB, and the gate of transistor MP2 and the source of transistor MP1 are connected to VA. In this circuit, if VA is larger than VB by at least one threshold voltage VTP of the transistor MP1 then VABMAX will be connected to VA through transistor MP1 and similarly, if VB is greater than VA by at least VTP, then VABMAX will be connected to VB through MP2. By connecting the N-type well region(s) 15 of the P-channel transistors in the input/output circuitry of a mixed-signal integrated circuit, the N-type well region 11 will be maintained at the higher of VA and VB. Unfortunately, the circuit of FIG. 2 exhibits a “dead-zone” of VTP volts and does not function effectively if one of the two supply voltages VA and VB is not greater than the other by at least VTP volts.
FIG. 3 shows another prior art implementation of supply voltage monitor circuit 15 of FIGS. 1E and 1F for maintaining the N-type well region 11 at the higher of VA and VB. Supply voltage monitor circuit 15 includes a conventional comparator 20, outputs of which are connected to gates of P-channel transistors MPD1 and MPD2, the drains and bulk electrodes of which are connected to conductor 15A. The sources of transistors MPD1 and MPD2 are connected to VA and VB, respectively. In the circuit of FIG. 3, if the supply voltage VA is turned on first to a voltage level that is high enough for the bias current generator to function properly, then the output voltage VABMAX on conductor 15A will select the higher of the VA and VB supply voltages without exhibiting a dead-zone such as that in the circuit of FIG. 2. However, the supply voltage monitor circuit of FIG. 3 has the disadvantage that the supply voltage VA must be turned on first before the comparator circuitry therein can function properly, because if VB is turned on first, the comparator 20 does not function and the circuit operation is equivalent to that of the circuit of FIG. 2.
Thus, there is an unmet need for a power supply voltage monitoring/control circuit that automatically connects an N-type well region of a CMOS integrated circuit to the highest of a plurality of supply voltages provided in the integrated circuit.
There is another unmet need for a power supply voltage monitoring/control circuit that automatically connects an N-type region or substrate of an integrated circuit to the highest of a plurality of supply voltages provided in the integrated circuit with minimum restriction on the magnitudes of the power supply voltages and the sequences in which the various power supply voltages must be turned on and off.
There is another unmet need for a power supply voltage monitoring/control circuit that continuously automatically connects an N-type well region of a CMOS integrated circuit to the highest of a plurality of supply voltages provided in the integrated circuit.
There is another unmet need for a power supply voltage monitoring/control circuit that avoids producing a “dead zone” in which the higher of a plurality of supply voltages is not reliably connected to an N-type well region of a CMOS integrated circuit.
There is another unmet need for a power supply voltage monitoring/control circuit that avoids the need users predetermined sequences to power up and power down multiple supply voltages applied to an integrated circuit.
There is another unmet need for a power supply voltage monitoring/control circuit that operates reliably irrespective of the magnitude of voltage differences between various supply voltages utilized in an integrated circuit including the monitoring/control circuit.